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| 128Mx72 bits Registered DDR SDRAM DIMM HYMD512G726A(L)4-M/K/H/L Document Title 128M x 72 bits Registered DDR SDRAM DIMM Revision History No. 0.1 0.2 1) Defined Target Spec. 1) Defined pin cap. spec. 2) Modified IDD current spec 3) Deleted preliminary. History Draft Date Jan. 2003 Feb. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Feb. 2004 1 128Mx72 bits Registered DDR SDRAM DIMM HYMD512G726A(L)4-M/K/H/L DESCRIPTION Hynix HYMD512G726A(L)4-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. HYMD512G726A(L)4-M/K/ H/L series consists of eighteen 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD512G726A(L)4-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD512G726A(L)4-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD512G726A(L)4-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES * * * * * * * 1GB (128M x 72) Registered DDR DIMM based on 128Mx4 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to reduce loading 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface * * * * * * * Fully differential clock operations (CK & /CK) with 125MHz/133MHz Programmable CAS Latency 2 / 2.5 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 8192 refresh cycles / 64ms ORDERING INFORMATION Part No. HYMD512G726A(L)4-M HYMD512G726A(L)4-K HYMD512G726A(L)4-H HYMD512G726A(L)4-L VDD=2.5V VDDQ=2.5V Power Supply Clock Frequency 133MHz (*DDR266 2-2-2) 133MHz (*DDR266A) Interface Form Factor SSTL_2 133MHz (*DDR266B) 125MHz (*DDR200) 184pin Registered DIMM 5.25 x 1.7 x 0.15 inch * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Feb. 2004 2 HYMD512G726A(L)4-M/K/H/L PIN DESCRIPTION Pin CK0, /CK0 CS0 CKE0 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS17 DM0~7 VDD /RESET Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Reset Enable Pin VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA WP VDDID DU NC FETEN Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O Write Protect Flag VDD Identification Flag Do not Use No Connection FET Enable PIN ASSIGNMENT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ DU DU VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Name A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 Vss A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Name VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS DU DU VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Name VSS DQ4 DQ5 VDDQ DQS9 DQ6 DQ7 VSS NC NC A13 VDDQ DQ12 DQ13 DQS10 VDD DQ14 DQ15 CKE1* VDDQ BA2* DQ20 A12 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 145 146 147 148 149 150 151 152 153 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 key VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44 Name VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DQS17 A10 CB6 VDDQ CB7 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Name /RAS DQ45 VDDQ /CS0 /CS1* DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC, FETEN* VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD * These are not used on this module but may be used for other module in 184pin DIMM family Rev. 0.2 / Feb. 2004 3 HYMD512G726A(L)4-M/K/H/L FUNCTIONAL BLOCK DIAGRAM VSS /RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS DQS9 DM D0 DQS10 /CS DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS DM D9 /CS DQS1 DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D1 DQS11 /CS DQ12 DQ13 DQ14 DQ15 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D10 /CS DQS2 DQ8 DQ9 DQ10 DQ11 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D2 DQS12 /CS DQ20 DQ21 DQ22 DQ23 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D11 DM DQS3 DQ16 DQ17 DQ18 DQ19 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D3 DQS13 /CS DM DQ28 DQ29 DQ30 DQ31 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS D12 DM DQS4 DQ24 DQ25 DQ26 DQ27 DQS I/O 0 I/O 1 I/O 2 I/O 3 D4 DQS14 /CS DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS D13 DM DQS5 DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D5 DQS15 /CS DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS D14 DQS6 DQ40 DQ41 DQ42 DQ43 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D6 DQS16 /CS DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS DM Serial PD D15 DM SCL WP A0 SA0 A1 SA1 A2 SA2 SDA DQS7 DQ48 DQ49 DQ50 DQ51 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D7 DQS17 /CS DQ60 DQ61 DQ62 DQ63 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS D16 VDDSPD DM DQS8 CB0 CB1 CB2 CB3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D8 CB4 CB5 CB6 CB7 DQS I/O 0 I/O 1 I/O 2 I/O 3 /CS VDDQ VDD VREF . D17 == VSS VDDID /CS0 BA0-BA1 A0-A12 /RAS /CAS CKE0 /WE /RCS0 -->/CS0 : SDRAMs D0-D17 RBA0-RBA1--> : BA0-BA1:SDRAMs D0-D17 RA0 -RA12 -->A0 - A12 : SDRAMs D0 - D17 /RRAS --> /RAS : SDRAMs D0 - D17 /RCAS --> /CAS : SDRAMs D0 - D17 RCKE0 --> CKE : SDRAMs D0 - D17 /RWE --> /WE : SDRAMs D0 - D17 . . . ...= . .. = . SPD D0 - D17 D0 - D17 D0 - D17 D0 - D17 Strap:see Note 4 R E G PCK /PCK /RESET CK0, /CK0 --------- PLL* * Wire per clock loading table/wiring diagrams Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ/DQS resistors should be 18 Ohms. 4. VDDID strap connections(for memory device VDD, VDDQ); Strap out :(open) : VDD=VDDQ Strap In (Vss) : VDD=VDDQ 5. Address and control resistors should be 22 Ohms Rev. 0.2 / Feb. 2004 4 HYMD512G726A(L)4-M/K/H/L ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature(ambient) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER Symbol 0 ~ +70 -55 ~ +125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 18 260 / 10 Rating o o Unit C C V V V mA W oC / Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V) Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage Symbol VDD VDDQ VIH VIL VTT VREF Min 2.3 2.3 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ Typ. 2.5 2.5 VREF 0.5*VDDQ Max 2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ Unit V V V V V V 3 2 1 Note Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ. AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ + 0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. Rev. 0.2 / Feb. 2004 5 HYMD512G726A(L)4-M/K/H/L AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns W W pF Rev. 0.2 / Feb. 2004 6 HYMD512G726A(L)4-M/K/H/L CAPACITANCE (TA=25oC, f=100MHz ) Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input / Output Capacitance Data Input / Output Capacitance A0 ~ A12, BA0, BA1 /RAS, /CAS, /WE CKE0 CS0 CK0, /CK0 DQ0 ~ DQ63, DQS0 ~ DQS17 CB0 ~ CB7 Pin Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIO1 CIO2 Min 5 5 5 5 7 7 7 Max 12 12 12 12 15 12 12 Unit pF pF pF pF pF pF pF Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT RT=50 Output Zo=50 VREF CL=30pF Rev. 0.2 / Feb. 2004 7 HYMD512G726A(L)4-M/K/H/L DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Add, CMD, /CS, /CKE CK, /CK Symbol Min. -2 Max 2 Unit Note Input Leakage Current ILI -4 ILO VOH VOL -5 VTT + 0.76 4 5 VTT - 0.76 uA 1 Output Leakage Current Output High Voltage Output Low Voltage uA V V 2 IOH = -15.2mA IOL = +15.2mA Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 2.7V 3. These values are device characteristics. Rev. 0.2 / Feb. 2004 8 HYMD512G726A(L)4-M/K/H/L DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Speed Parameter Symbol Test Condition -M One bank; Active - Precharge ; tRC=tRC(min); tCK= tCK(min) ; DQ,DM and DQS inputs changing twice per clock cycle ; address and control inputs changing once per clock cycle One bank ; Active - Read - Precharge ; Burst Length = 2 ; tRC=tRC(min); tCK= tCK(min) ; address and control inputs changing once per clock cycle All banks idle ; Power down mode ; CKE= Low, tCK= tCK(min) /CS = High, All banks idle ; tCK= tCK(min) ; CKE = High ; address and control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM /CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS and DM One bank active ; Power down mode ; CKE= Low, tCK= tCK(min) /CS= HIGH; CKE = HIGH; One bank; ActivePrecharge; tRC = tRAS(max); tCK = t CK (max); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst = 2 ; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK= tCK (min); IOUT = 0mA Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (min); DQ, DM, and DQS inputs changing twice per clock cycle tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh CKE =< 0.2V; External clock on; tCK = tCK(min) Normal Low Power 7490 Unit Note -K -H -L Operating Current IDD0 2990 2810 2810 2630 mA Operating Current IDD1 3530 3350 3350 3350 mA Precharge Power Down Standby Current IDD2P 830 mA Idle Standby Current IDD2F 1280 mA Idle Quiet Standby Current Active Power Down Standby Current IDD2Q 1280 mA IDD3P 920 mA Active Standby Current IDD3N 1370 mA Operating Current IDD4R 4250 4250 4250 3890 mA Operating Current IDD4W 4250 4250 4250 3890 mA Auto Refresh Current IDD5 5030 5030 5030 4670 mA 440 395 7490 7490 6050 mA mA mA Self Refresh Current Operating Current Four Bank Operation IDD6 IDD7 Four bank interleaving with BL=4 Refer to the following page for detailed test condition Rev. 0.2 / Feb. 2004 9 HYMD512G726A(L)4-M/K/H/L AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew CL = 2.5 CL = 2 Symbol tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL -M(DDR266 2-2-2) Min 60 75 45 tRCD or tRP min 15 15 1 15 15 1 2+(tRP/ tCK) 7.5 7.5 0.45 0.45 -0.75 -0.75 tHPmin -tQHS tCH/L min Max 120K 12 12 0.55 0.55 0.75 0.75 0.5 0.75 -K(DDR266A) Min 65 75 45 tRCD or tRP min 20 15 1 20 15 1 5 7.5 7.5 0.45 0.45 -0.75 -0.75 tHPmin -tQHS tCH/L min Max 120K 12 12 0.55 0.55 0.75 0.75 0.5 0.75 -H(DDR266B) Min 65 75 45 tRCD or tRP min 20 15 1 20 15 1 5 7.5 10 0.45 0.45 -0.75 -0.75 tHPmin -tQHS tCH/L min Max 120K 12 12 0.55 0.55 0.75 0.75 0.5 0.75 -L(DDR200) Min 70 80 50 tRCD or tRP min 20 15 1 20 15 1 (tWR/tCK) + (tRP/tCK) Max 120K 12 10 0.55 0.55 0.75 0.75 0.6 0.75 Unit Note ns ns ns ns ns ns CK ns ns CK CK ns ns CK CK ns ns ns ns ns ns ns ns 1, 10 1,9 10 15 16 tCK tCH tCL tAC 8 12 0.45 0.45 -0.75 -0.75 tHPmin -tQHS tCH/L min - DQS-Out edge to Clock edge Skew tDQSCK DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Valid Data Output Window Data-out high-impedance window from CK, /CK Data-out low-impedance window from CK, /CK Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) tDQSQ tQH tHP tQHS tDV tHZ tQH-tDQSQ -0.75 0.75 tQH-tDQSQ -0.75 0.75 tQH-tDQSQ -0.75 0.75 tQH-tDQSQ -0.8 0.8 tLZ -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 2,3,5 ,6 2,3,5 ,6 2,4,5 ,6 tIS tIH tIS 0.9 0.9 1.0 - 0.9 0.9 1.0 - 0.9 0.9 1.0 - 1.1 1.1 1.1 - ns ns ns Rev. 0.2 / Feb. 2004 10 HYMD512G726A(L)4-M/K/H/L AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -M(DDR2662-2-2) Parameter Symbol Min Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Note : 1. 2. 3. 4. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. For command/address input slew rate >=1.0V/ns For command/address input slew rate >=0.5V/ns and <1.0V/ns This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 5. 6. 7. 8. 9. CK, /CK slew rates are >=1.0V/ns These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 11 Delta tIS ps 0 +50 +100 Delta tIH ps 0 0 0 tIH tIPW tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI 1.0 2.2 0.35 0.35 0.75 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 200 Max 1.28 1.1 0.6 0.6 7.8 Min 1.0 2.2 0.35 0.35 0.75 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 200 Max 1.25 1.1 0.6 0.6 7.8 Min 1.0 2.2 0.35 0.35 0.75 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 200 Max 1.25 1.1 0.6 0.6 7.8 Min 1.1 2.5 0.35 0.35 0.75 0.6 0.6 2 0.9 0.4 0 0.25 0.4 2 200 Max 1.25 1.1 0.6 0.6 7.8 ns ns CK CK CK ns ns ns CK CK CK CK CK CK CK us 8 6,7, 11~13 6,7, 11~13 2,4,5, 6 6 -K(DDR266A) -H(DDR266B) -L(DDR200) Unit Note - continued - Rev. 0.2 / Feb. 2004 HYMD512G726A(L)4-M/K/H/L 10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. 11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 Delta tDS ps 0 +75 +150 Delta tDH ps 0 +75 +150 12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level mV +280 Delta tDS ps +50 Delta tDH ps +50 13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) ns/V 0 +/-0.25 +/- 0.5 Delta tDS ps 0 +50 +100 Delta tDH ps 0 +50 +100 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. 15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock 16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tCK. Rev. 0.2 / Feb. 2004 12 HYMD512G726A(L)4-M/K/H/L SIMPLIFIED COMMAND TRUTH TABLE Command Extended Mode Register Set Mode Register Set Device Deselect H No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit L H L H Entry Precharge Power Down Mode Exit L H L H Active Power Down Mode Entry Exit H L L L H V X V V X 1 1 H X H X H X 1 1 H L L H H X H X H X X 1 1 H X H X H X 1 H H H X H L L L L H H L L X H L L X L H H X X 1 X L L H L X L X X V 1 1 1 1 X L H L L CA H H X X L H L H CA H L V 1,4 1,5 H X X L L H L H H H H RA L V 1,3 1 V 1 1 CKEn-1 H H CKEn X X /CS L L H /RAS L L X /CAS L L X /WE L L X X 1 ADDR A10/ AP OP code OP code BA Note 1,2 1,2 ( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. DM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.2 / Feb. 2004 13 HYMD512G726A(L)4-M/K/H/L PACKAGE DIMENSIONS Front 133.35 5.25 131.35 5.171 128.95 5.077 (2X)4.00 .157 43.18 1.7 10.0 .394 Register PLL Register (2) 0 2.5 0.098 Back 3.99 .157max (Front) 1.27+/-0.10 0.05+/-0.004 Rev. 0.2 / Feb. 2004 4.24 .167 17.80 .700 3.0 .118 Side 14 SERIAL PRESENCE DETECT SPD SPECIFICATION (128Mx72 Registered DDR DIMM) Rev. 0.2 / Feb. 2004 15 HYMD512G726A(L)4-M/K/H/L SERIAL PRESENCE DETECT Byte Function Description M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Number of Bytes written into serial memory at module manufacturer Total number of Bytes in SPD device Fundamental memory type Number of row address on this assembly Number of column address on this assembly Number of physical banks on DIMM Module data width Module data width (continued) Module voltage Interface levels(VDDQ) DDR SDRAM cycle time at CAS Latency=2.5(tCK) Module configuration type Refresh rate and type Primary DDR SDRAM width Error checking DDR SDRAM data width Minimum clock delay for back-to-back random column address(tCCD) Burst lengths supported Number of banks on each DDR SDRAM CAS latency supported CS latency WE latency DDR SDRAM module attributes DDR SDRAM device attributes : General DDR SDRAM cycle time at CL=2.0(tCK) DDR SDRAM access time from clock at CL=2.0(tAC) DDR SDRAM cycle time at CL=1.5(tCK) DDR SDRAM access time from clock at CL=1.5(tAC) Minimum row precharge time(tRP) Minimum row activate to row active delay(tRRD) Minimum RAS to CAS delay(tRCD) Minimum active to precharge time(tRAS) Module row density Command and address signal input setup time(tIS) Command and address signal input hold time(tIH) Data signal input setup time(tDS) Data signal input hold time(tDH) 0.9ns 0.9ns 0.5ns 0.5ns 0.9ns 0.9ns 0.5ns 0.5ns 15ns 15ns 15ns 45ns 20ns 15ns 20ns 45ns 1GB 0.9ns 0.9ns 0.5ns 0.5ns 1.1ns 1.1ns 0.6ns 0.6ns 90h 90h 50h 50h 7.5ns 7.5ns 7.5ns ECC 7.8us & Self refresh x4 x4 1 CLK 2,4,8 4 Banks 2, 2.5 0 1 Registered, PLL +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock Out 7.5ns 20ns 15ns 20ns 45ns 20ns 15ns 20ns 50ns 3Ch 3Ch 3Ch 2Dh 10ns 10ns +/-0.8ns 75h 75h +/-0.75ns +/-0.75ns +/-0.75ns K H L M K 80h 08h 07h 0Dh 0Ch 01h 48h 00h 04h 8ns +/-0.8ns 75h 75h 75h 75h 02h 82h 04h 04h 01h 0Eh 04h 0Ch 01h 02h 26h C0h 75h 75h 00h 00h 50h 3Ch 50h 2Dh 01h 90h 90h 50h 50h 00h 70ns 80ns 12ns 0.6ns 0.75ns 3Ch 4Bh 30h 32h 75h 41h 4Bh 30h 32h 75h 00h 00h 5Dh 8Ah B5h 4Fh 41h 4Bh 30h 32h 75h 46h 50h 30h 3Ch 75h 90h 90h 50h 50h B0h B0h 60h 60h 50h 3Ch 50h 2Dh 50h 3Ch 50h 32h A0h 75h A0h 80h 2 2 2 2 75h 75h 80h 80h 2 2 7.5ns 1 1 H L Bin Sort : M(DDR266 2-2-2@CL=2),K(DDR266A@CL=2) H(DDR266B@CL=2.5), L(DDR200@CL=2) Function Supported Hexa Value Note 128 Bytes 256 Bytes DDR SDRAM 13 12 1Bank 72 Bits SSTL 2.5V DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.75ns +/-0.75ns +/-0.75ns 36~40 Reserved for VCSDRAM 41 42 43 44 45 Minimum active / auto-refresh time ( tRC) Minimum auto-refresh to active/auto-refresh command period(tRFC) Maximum cycle time (tCK max) Maximim DQS-DQ skew time(tDQSQ) Maximum read data hold skew factor(tQHS) 60ns 75ns 12ns 0.5ns 0.75ns Undefined 65ns 75ns 12ns 0.5ns 0.75ns 65ns 75ns 12ns 0.5ns 0.75ns 46~61 Superset information(may be used in future) 62 63 SPD Revision code Checksum for Bytes 0~62 Undefined Initial release - Rev. 0.2 / Feb. 2004 16 HYMD512G726A(L)4-M/K/H/L SERIAL PRESENCE DETECT Function Supported Byte 64 65~71 Function Description M Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code K H L M K ADh 00h 0*h 1*h 2*h 3*h 4*h 5*h 48h 59h 4Dh 44h 35h 31h 32h 47h 37h 32h 36h 41h 34h 2Dh H Blank Blank Undefined Undefined L 4Dh 4Bh 20h 20h 00h 00h 3 3 4 5 5 48h 4Ch H L Hynix JEDEC ID Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area H Y M D 5 1 2 G 7 2 6(8K refresh,4Bank) A 4 `-' M K Hexa Value Note 72 Manufacturing location 6 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88~90 91 92 93 94 95~98 99~127 Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) Manufacture part number (DDR SDRAM) Manufacture part number(Memory density) Manufacture part number(Module Depth) ------- Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -------Manufacture part number(Data width) Manufacture part number(Refresh, # of Bank.) Manufacture part number(Component Generation) Manufacture part number(Component configuration) Manufacture part number(Hyphen) Manufacture part number(Minimum cycle time) Manufacture part number(T.B.D) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may be used in future) 128~255 Open for customer use Note : 1. The bank address is excluded 2. This value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix's own Module Serial Number System 5. These bytes undefined and coded as `00h' 6. Refer to Hynix Web Site Byte 85~86, Low Power Part Function Supported Byte # 85 86 Function Description M Manufacture part number(Low power part) Manufacture part number(Component Configuration) K L 4 H L M K 4Ch 34h H L Hexa Value Note Rev. 0.2 / Feb. 2004 17 |
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